1. Field of the Invention
The present invention relates to an output buffer circuit having a slew rate increasing part configured with a switching element. The output buffer circuit can obtain an output voltage having a high slew rate even though a smaller amount of a bias current than that required in a conventional output buffer is used. Therefore, the output buffer circuit can reduce power consumption.
2. Description of the Related Art
In general, display fields are considered as high technology fields that are promising in electronic industries. A lot of liquid crystal displays (LCDs) and plasma display panels (PDPs) have been manufactured.
As the next generation technologies, various kinds of displays devices are actively under development. Among them, spatial optical modulators (SOMs) are being most actively developed. Even though SOM driver ICs have the output resolution of 8 bits, it is expected that they will have the output resolution of 10 bits or more in the near future. Therefore, there is a demand for a high-speed and high-precision driver IC that can drive the SOM driver ICs having the output resolution of 10 bits or more.
A high slew rate is required to maintain high-speed and high-precision characteristic. The slew rate means a rising variation of an output signal per unit time with respect to a step variation of a control input signal. Thus, a driver IC having a high slew rate is required to transfer an image signal more accurately in a predefined data transfer time.
FIG. 1 is a circuit diagram of a modeled output buffer 100 according to the related art, and FIG. 2 is a waveform diagram of an input voltage signal and an output voltage signal according to the related art.
Referring to FIGS. 1 and 2, the output buffer 100 according to the related art can be modeled with a large-capacity capacitor Coff of 50 pF or more.
However, when the slew rate of the output buffer 100 is low, the capacitor Coff is not fully charged during a predefined data transfer time t, so that an image signal is delayed. Consequently, the image signal cannot be accurately transferred in the predefined data transfer time t.
As illustrated in FIG. 2, in the case of the output buffer with a low slew rate, when an upslewing input signal is applied during the predefined data transfer time t, an output image signal (a) does not have a predetermined amplitude. Likewise, when a downslewing input signal is applied, an output image signal (b) does not have a predetermined amplitude.
To solve this problem, the slew rate of the output buffer should be improved. If the slew rate of the circuit increases, the output voltage becomes a little higher when the upslewing input signal is applied. On the other hand, the output voltage becomes a little lower when the downslewing input signal is applied. Therefore, the image signal can be transferred more accurately in the predefined data transfer time t.
FIG. 3 is a circuit diagram of an output buffer circuit according to the related art. Referring to FIG. 3, the output buffer circuit according to the related art includes a compensation capacitive load CC, an input part 301a-301e, an output part 302, and a current source 303.
Differential input voltage signals are applied to two input terminals of the input part 301a to 301e. 
The differential input voltage means a difference between voltages applied to the two input terminals. The output buffer circuit according to the related art employs a differential input circuit scheme that operates only in response to the difference between the voltages applied to the two input terminals.
In addition, the output part 302 increases a gain of the differential input voltages and the current source 303 biases the output part 302.
A slewing operation of the output buffer circuit according to the related art will be described below with reference to FIG. 3.
In FIG. 3, ISS is a bias current of the input part 301a-301e, IP is a current that is biased through the current source 303 to the output part 302, and gm is a mutual conductance of a MOS transistor. When the differential input voltage applied to the input part 301a-301e is more than ISS/gm, that is, when the slewing differential input voltage is applied, some transistors of the input part 301a-301e are turned on, and some transistors are turned off. Therefore, ISS flows only through some transistors.
The above-described operations are divided into two cases: the first case where the upslewing input voltage is applied, and the second case where the downslewing input voltage is applied.
When the upslewing input voltage is applied, that is, when a gate voltage of the first PMOS transistor 301a is higher than that of the second PMOS transistor 301b by more than ISS/gm, only the second PMOS transistor 301b is turned on, so that ISS flows only through the second PMOS transistor 301b. 
Therefore, ISS flows through the second NMOS transistor 301e connected to the second PMOS transistor 301b. Because the magnitude of the current biased through the current source 303 to the output part 302 is fixed to IP, ISS is supplied through the discharge of the compensation capacitive load CC. Thus, ISS also flows through the first NMOS transistor 301d, which has a mirror relationship with the second PMOS transistor 301e. 
ISS flows through the ground of the first NMOS transistor 301d, so that a drain voltage of the first NMOS transistor 301d is dropped. Consequently, the drain voltage of the output part 302 is increased and the voltage of the output terminal “out” is increased.
When the downslewing input voltage is applied, that is, when the gate voltage of the first PMOS transistor 301a is lower than that of the second PMOS transistor 301b by more than ISS/gm, only the first PMOS transistor 301a is turned on, so that ISS flows only through the first PMOS transistor 301a. 
Therefore, ISS does not flow through the second NMOS transistor 301e, and ISS does not flow through the first NMOS transistor 301d, which has a mirror relationship with the second NMOS transistor 301e. 
Because the magnitude of the current biased through the current source 303 to the output part 302 is fixed to IP, ISS transferred through only the first PMOS transistor 301a is charged to the compensation capacitive load CC.
Therefore, the drain voltage of the first NMOS transistor 301d is increased. Consequently, the drain voltage of the output part 302 is dropped and the voltage of the output terminal “out” is dropped.
However, when the slew rate is increased due to the high-speed and high-precision characteristics, the output buffer circuit according to the related art consumes much power. The reason is that the slew rate corresponds to the value given by dividing ISS by the capacitance of the compensation capacitive load CC and thus is proportional to ISS, as expressed as Equation (1) below.Slew rate=ISS/CC  (1)
That is, because the compensation capacitive load CC must be charged and discharged so as to increase the slew rate, a large amount of ISS should be used. Consequently, ISS having a sufficient magnitude has to flow through the circuit during all time when the input voltage is applied, as well as during the slewing, thus increasing the power consumption.